Efficient common mode suppression for transmission systems

ABSTRACT

In some aspects, the disclosure is directed to methods and systems for an amplifier having common mode feedback inputs. The inputs are coupled to various points within an amplifier wherein a first set of directly coupled common mode feedback inputs join the amplifier one or more nodes, and a second set of capacitively coupled common mode feedback inputs are joined to the amplifier at one or more different nodes.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to U.S. Provisional PatentApplication No. 63/335,913, filed Apr. 28, 2022, the entire contents ofwhich are incorporated by reference in their entirety.

FIELD OF THE DISCLOSURE

This disclosure generally relates to systems and methods for common modesuppression. In particular, this disclosure relates to systems andmethods for suppressing wideband common mode interference at anamplifier.

BACKGROUND OF THE DISCLOSURE

Modern electronic devices continue to increase in complexity,interconnectivity, and functionality. For example, industrial machines,automobiles, and personal electronic devices continue to form networks.The internet of things (IOT) is one example of the increasinginterconnectivity of devices.

In addition to the increasing interconnectivity of devices, datacontinues to be of increasing importance. For example, in automotive andindustrial systems, as well as personal devices such as wearabledevices, frequent data collection and transmission may enable variousprognostics and analytics of machinery, vehicles, and people. Such datacollection may be over a wide variety of wired and wirelesscommunication channels such as various Ethernet protocols, USB, CAN,Bluetooth, Zigbee, and numerous other protocols, each of which may haveone or more associated physical layer standards which mustinter-operate.

Although substantial efforts are made to prevent inter-deviceinterference, various protocols may sometimes interfere withcommunications channels. For example, a wired or wireless communicationchannel may couple to another communication channel, causinginterference. In additional to aggressor communication channels, variousenvironmental interferences, such as ignition coils, motors includingstepper motors, bus bars, etc. may couple to a communications channeland thereby degrade performance. Although sophisticated strategies andcircuits are used to minimize the impact of these issues, advances areneeded in the state of the art.

SUMMARY OF THE DISCLOSURE

Common mode signals can ride along differential pairs such that thedifferential signal is maintained. However, various amplifier canexhibit non-linear amplification of shifted signals, or otherwiseamplify common mode signals. Such amplification can result in incorrectregistering of bit values, an amplification of common mode noise whichcan couple into further circuits, or damage to a circuit, wherein avoltage level can exceed a limit. A dedicated common mode amplifier canprovide common mode suppression, however, such an amplifier can beduplicative of a main differential amplifier. According to systems andmethods of the present disclosure, various constituent portions of acommon mode signal can be injected into the main amplifier to suppresscommon mode signals, reusing existing circuits to reduce die area,energy use, complexity, and the like relative to systems employingdedicated common mode suppression amplifiers.

An embodiment of the present disclosure is directed to an amplifier. Theamplifier includes a first amplifier stage. The first amplifier stageincludes a pair of differential input ports configured to receive adifferential input signal at a first pair of gates of a first pair oftransistors. The first amplifier stage includes a pair of referenceinput ports configured to receive a common mode reference at a secondpair of gates of a second pair of transistors. The first amplifier stageincludes a first pair of inter-stage outputs configured to deliver apair of amplified signals from the first amplifier stage to a pair ofgates of a third pair of transistors of a second amplifier stage. Theamplifier includes a second amplifier stage. The second amplifier stageincludes a first pair of current sources. The second amplifier stageincludes a second pair of current sources. The second amplifier stageincludes a feedback network coupled between an output of the amplifierand a stage of the amplifier. The feedback network includes a first pairof feedback inputs directly coupled to the first amplifier stage, or asecond pair of feedback inputs capacitively coupled to the first pair ofcurrent sources, or a third pair of feedback inputs capacitively coupledto the second pair of current sources.

Another embodiment of the present disclosure is directed to a system.The system includes a first amplifier stage of an amplifier. The firstamplifier stage includes a pair of differential input ports configuredto receive a differential input signal at a first pair of gates of afirst pair of transistors. The first amplifier stage includes a pair ofreference input ports configured to receive a common mode reference at asecond pair of gates of a second pair of transistors. The firstamplifier stage includes a first pair of inter-stage outputs configuredto deliver a pair of amplified signals from the first amplifier stage toa pair of gates of a third pair of transistors of a second amplifierstage. The system includes the second amplifier stage. The secondamplifier stage includes a first pair of high side current sources. Thesecond amplifier stage includes a second pair low side of currentsources. The second amplifier stage includes a feedback network coupledbetween an output of the amplifier and a stage of the amplifier. Thefeedback network includes a first pair of feedback inputs directlycoupled to the first amplifier stage. The feedback network includes asecond pair of feedback inputs capacitively coupled to the first pair ofhigh side current sources. The feedback network includes a third pair offeedback inputs capacitively coupled to the second pair of low sidecurrent sources.

Yet another embodiment of the present disclosure is directed to amethod. The method includes receiving, at a first stage of adifferential amplifier a differential data signal at first input gatesof first transistors of respective portions of the first stage. Themethod includes receiving, at a first stage of a differential amplifier,a common mode reference signal at second input gates of secondtransistors of respective portions of the first stage. The methodincludes receiving, at a first stage of a differential amplifier, afirst differential feedback input at third inputs intermediate to thefirst transistors and the second transistors. The method includesgenerating, by the first stage of the differential amplifier, adifferential inter-stage output based on the differential data signal,the common mode reference signal, and the first differential feedbackinput. The method includes receiving, by the second stage of thedifferential amplifier, a second differential feedback input at a highside current source at respective portions of the second stage. Themethod includes receiving, by the second stage of the differentialamplifier, a third differential feedback input at a low side currentsource at respective portions of the second stage. The differentialinter-stage output can be intermediate to the high side current sourceand the low side current source at respective portions of the secondstage. The method includes generating, by the second stage of thedifferential amplifier, an output based on the differential inter-stageoutput, the second differential feedback input, and the thirddifferential feedback input.

BRIEF DESCRIPTION OF THE DRAWINGS

Various objects, aspects, features, and advantages of the disclosurewill become more apparent and better understood by referring to thedetailed description taken in conjunction with the accompanyingdrawings, in which like reference characters identify correspondingelements throughout. In the drawings, like reference numbers generallyindicate identical, functionally similar, and/or structurally similarelements.

FIG. 1 is an illustration of a circuit including a differentialamplifier driving a transmission line coupled to common modeinterference, according to some implementations.

FIG. 2 is an illustration of a differential amplifier having a primaryand additional stage, according to some implementations.

FIG. 3 is an illustration of a circuit depicting a directly coupledcommon mode feedback path, according to some implementations.

FIG. 4 is an illustration of a circuit depicting a capacitively coupledcommon mode feedback path, according to some implementations.

FIG. 5 is an flow diagram for a method for common mode suppression,according to some implementations.

FIG. 6A is a block diagram depicting an embodiment of a networkenvironment including one or more access points in communication withone or more devices or stations; and

FIGS. 6B and 6C are block diagrams depicting embodiments of computingdevices useful in connection with the methods and systems describedherein.

The details of various embodiments of the methods and systems are setforth in the accompanying drawings and the description below.

DETAILED DESCRIPTION

The following IEEE standard(s), including any draft versions of suchstandard(s), are hereby incorporated herein by reference in theirentirety and are made part of the present disclosure for all purposes:WiFi Alliance standards and IEEE 802.3 standards including but notlimited to IEEE P802.3i™; IEEE P802.3ab™; IEEE P802.3bw™. Although thisdisclosure may reference aspects of these standard(s), the disclosure isin no way limited by these standard(s). Although this disclosure canreference aspects of these standard(s), the disclosure is in no waylimited by these standard(s). For example, various communication orpower applications may include amplifiers employing the systems andmethods disclosed herein.

For purposes of reading the description of the various embodimentsbelow, the following descriptions of the sections of the specificationand their respective contents can be helpful:

-   -   Section A describes embodiments of systems and methods for        common mode suppression; and    -   Section B describes a network environment and computing        environment which may be useful for practicing embodiments        described herein.

A. Common Mode Suppression

A line driver may comprise an amplifier to condition a signal, such as asignal drive strength or a single voltage. In communication channels,communication links may be victimized by aggressor/disturber signalscoupled to the line. For example, a network may comprise an Ethernetnetwork (e.g., an automotive Ethernet network), having one or moretwisted pairs for differential communication. Various common modesignals may couple into Ethernet cables. For example, power supplies ofone or more devices on the network may couple directly to the cables,such as by riding along a shielding thereof, even where isolation isprovided (e.g., by inadequate isolation between two various groundplanes). Networks protocols or implementations forgoing port isolationmay further contribute to such contributions. Moreover, even properlyisolated ports may couple noise from environmental factors such asmotors, power cabling, or communications cabling. Indeed, in manyenvironments, various cables may be routed through similar paths (e.g.,due to mechanical constraints) resulting in a large surface area foraggressor/disturber signals coupling to the transmission line.

Because a wide variety of signals may couple to the transmission line, awide variety of frequencies must be accounted for. For example, theoutput from an ignition coil or a lightning strike may approximate aDirac function, whereas a single speed motor or an associated bus barmay be associated with a fixed frequency (e.g., 50 Hz). In someembodiments, an aggressor signal may be known and characterized, inwhich case rejection of certain frequencies may be of greater interestthan others. In some embodiments, such as a vehicle integrating variouselectronic devices, it may be difficult or impractical to characterizeall potential aggressor signals. At sufficient amplitude, common modesignals may interfere with communication, and/or may result in hardwarefailure (e.g., by exceeding an isolation voltage associated with acommunications port).

Thus, it may be desirable to provide a plurality of feedback inputs forcommon mode signals into an amplifier, to allow for the rejection ofsaid common mode signals. A “feedback input” may refer to a conductiveelement conveying an output signal to an input of a circuit. Forexample, the output signal can provide an indication of the performanceof the circuit, or a transformation applied to the circuit by anaggressor signal. By selectively introducing common mode signals, suchrejection/suppression may be achieved using existing components of theline-driver amplifier. For example, the systems and methods of thepresent disclosure may omit a dedicated common mode amplifier tosuppress common mode signals. Such an omission may reduce a surface areaof a semiconductor die, lower power use, reduce complexity, reduce anexposure of active circuit elements to transient signals which candegrade a performance thereof, and the like. For example, a circuit caninclude inputs to directly couple low frequency common mode feedback,and separate inputs to capacitively couple higher frequency feedback.

FIG. 1 depicts an embodiment of a circuit 100 including an amplifier 110driving a transmission line 125 coupled to a common mode interface 140.The depicted amplifier 110 is a differential amplifier which outputs adifferential signal 120 comprising a positive output 120A component andnegative output 120B component. The positive and negative reference areintended merely to describe the signals with reference to each other.Although in many embodiments, the positive and negative signals may alsobe positive and negative in reference to one or more ground or otherreference signals, such embodiments are not limiting.

A termination network 130 can intermediate an output of an amplifier 110from a transmission line 125 such that the output signal may passthrough a termination network 130. For example, the amplifier output maypass through a near end termination network having a terminationimpedance approximating the characteristic impedance of the transmissionline, or to a far end termination network having a similar terminationimpedance. For example, the termination impedance may be 50, 90, or 100Ω. The example termination impedances enumerated herein are merelyillustrative, and the termination impedance may comprise a wide varietyof networks comprising further reactive components. Thus, common modesignals 140 may be conditioned (e.g., damped) by a termination networksuch that the common mode signal coupled to a cable or othertransmission line 125 (e.g., a shielded or unshielded twisted pair cablefor a differential signal, wireless link, or other transmission line)may be different in amplitude or other characteristic relative to thecommon mode signal as seen at the output of the amplifier 110.

Some embodiments may omit the termination network 130. For example, theamplifier 110 may drive a transmission line 125 without anintermediating termination network 130. For example, a connectionbetween collocated printed circuit board assemblies, or within a printedcircuit board assembly may omit a termination network between transmitand receive signals based on a required signal integrity. In general, anamplifier generating or receiving a waveform having a relatively slowslew rate, or which is connected at distance permitting any signals tobe registered prior to the receipt of reflections, may omit atermination network 130.

Common mode signals (e.g., the depicted incoming common mode disturber140A or reduced common mode signal 140B) may be coupled onto thetransmission line 125 from a variety of sources. For example, aggressorcommunication lines may couple onto a transmission cable (e.g., to thesignal conductors directly, to a cable shield which is, in turn coupledto the signal conductors). Such aggressor lines may be associated withthe same communications link (e.g., may be additional differential pairsof a same link, including certain Ethernet, PCIe, and USB topographies).Aggressor lines may be different communication channels, or may be othersources such as power supplies, power cabling, lighting strikes, othertransient environmental interference, etc. In many embodiments, thetransmission lines may be configured to avoid differential interferencebetween the lines. For example, a differential pair may be routedsymmetrically and adjacently; pairs of the differential pair may beconfigured as a twisted pair, etc. Although such measures may mitigatedifferential mode interference between the conductors of thedifferential pair, they may also result in undesirable common modecoupling to the differential pair. This common mode signal may, in someembodiments, be an aggressor signal to other communication links, leadto differential mode issues due to amplifier non-linearity, exceedregulatory emission requirements, etc. Thus, it may be desirable toadjust an output of the amplifier 110 to negate a common mode signal140B coupled thereto.

An amplifier 110 configured to output a differential signal may includefeedback to prevent differential mode disturbances. For example, adifferential feedback impedance network 150A may join the positiveoutput 120A with a first input 160A. A second feedback impedance 150Bmay join the negative output 120B with a second input 160B. In manyembodiments, the first feedback impedance 150A and second feedbackimpedance 150B are equal, such that the differential feedback issymmetrical.

The depicted circuit includes a common mode feedback portion of thecircuit comprising a common mode feedback impedance network 150C toconvey an indication of the common mode signal coupled to the line tothe amplifier 110, and improve the common mode rejection of theamplifier 110. The common mode feedback impedance network 150C mayintroduce a common mode signal 140 from the near side of the terminationnetwork 130 to the amplifier 110, such that the amplifier 110 maycompensate for the common mode signal 140. Advantageously, the inclusionof the common mode feedback impedance network 150C inside of thetermination may avoid various signal integrity issues along thetransmission line 125 (e.g., reflections from the common mode feedbackimpedance network 150C). In some embodiments, the common mode feedbackimpedance network 150C may be coupled outside of the termination network130 which may receive a signal of larger amplitude or drive strength.

The depicted common mode feedback impedance network 150C includes a pairof resistors 152 configured to introduce low frequency (e.g., directcurrent (DC)) common mode feedback to the amplifier 110. Such aresistive feedback coupling may be termed “directly coupled” or “DCcoupled” herein. In some embodiments, a plurality of resistor pairs 152may be included to introduce the feedback to multiple points within theamplifier. An output from a single pair of resistors 152 may beintroduced at multiple points within the amplifier. In some embodiments,the resistor pair 152 may be supplemented (e.g., by an inductor) toreject high frequency signals through the DC coupled path. An amplifier110 may couple lower frequency feedback separately from higher frequencyfeedback, such as according to the bandwidth of the amplifier 110, or ofone or more stages of the amplifier 110. A “stage” of an amplifier mayrefer to a portion of the amplifier providing a gain for a signal, whichcan include one or more transistors. For example, a first stage mayprovide a first gain to a signal, and a second stage may provide asecond gain to the signal such that total signal gain can be determinedby multiplying the first and second gain. A gain may be a current gain,voltage gain, or so forth. Stages may have varying bandwidths such thata first gain may apply to a first portion of the signal, and the secondgain may apply to a second portion of the signal.

The common mode feedback impedance network 150C also comprises a pair ofcapacitors 154 configured to introduce relatively high frequency signals(which may be referred to herein, as “capacitively coupled”) to theamplifier 110. The pair of capacitors 154 (and/or the resistors 152) maybe configured (e.g., based on a capacitance/resistance value) tointroduce signals of various frequencies into the amplifier 110. In someembodiments, a plurality of pairs of capacitors 154 may introducerelatively high frequency signals to various positions within theamplifier 110, and/or it's associated ports. The various capacitor pairs154 may be equal or may be different (e.g., to better couple desiredfrequency ranges to various positions within the amplifier 110.).Alternatively, or in addition, an output from a single pair ofcapacitors 154 may be introduced at multiple points within theamplifier.

According to various embodiments, components (e.g., capacitors,resistors, inductors, or the like) of the common mode feedback impedancenetwork 150C can include discrete components or may be integral to asame device as the amplifier 110. For example, a semiconductor deviceincluding the amplifier 110 can include a plurality of ports tointerface with the common mode feedback impedance network 150C,differential feedback impedance network 150A, or the like. Asemiconductor device including the amplifier 110 can include at least aportion of the feedback impedance network 150C and the differentialfeedback impedance network 150A, which may reduce a number of ports,pins, landings or other terminals of the semiconductor device. Forexample, the feedback networks can be instantiated in a same silicondie, in an integrated passive device (IPD) or the semiconductor device,or the like.

In some embodiments, the common mode feedback impedance network 150C mayinclude additional or fewer component. For example, the feedback signalsmay include an amplifier, buffer, or various filters (e.g., high pass,low pass, band pass, band reject) intended to control the frequency offeedback delivered to an amplifier. For example, if a common mode signalof 60 Hz is desired (e.g., to transmit a signal over an AC power line),the common mode feedback impedance network 150C may comprise a band passfilter to reject feedback from 40 Hz to 75 Hz. Some embodiments of thecommon mode feedback impedance network 150C may omit an amplifier, whichmay reduce a component count for discrete circuits, or a surface area,transistor count, or power usage for semiconductor devices. As describedabove, various components can be integral to a same device as theamplifier, or can be connected thereto. “Integral” may refer to acomponent being integrated into, and not readily separable from, alarger assembly. For example, various components disposed on a samesemiconductor die, semiconductor package, or circuit board may bereferred to as integral to the semiconductor die, semiconductor package,or circuit board, respectively.

FIG. 2 illustrates an embodiment of an amplifier 200 having a primarystage 210 and an additional stage 220. For example, the amplifier 200may be the amplifier 110 depicted in FIG. 1 . The amplifier 200 may be aclass AB amplifier, a class B amplifier (not depicted), or anotheramplifier type. The primary stage 210 (e.g., input stage) can receive aninput signal at input signal ports 202 and a separate common modereference at common mode reference input ports 204. A “common modereference” may refer to a reference voltage level which is sharedbetween a pair of inputs or outputs, according to some embodiments. Forexample, the common mode reference may be a ground or a DC offsettherefrom. The primary stage amplifier output 206 can electricallycouple the output of the primary stage 210 to one or more additionalstages 220 of the amplifier. For example, the additional stages 220 caninclude an output stage, and zero or more intermediate stages. Forexample, as depicted, the primary stage amplifier output 206 couples toan additional stage 220 comprising a first 220A and second additionalstage portion 220B for a respective signals of a differential pair. Thefirst 220A and second additional stage portions 220B may electricallycouple the outputs thereof to a first 230A and second output terminal230B at an output stage of the amplifier. Although not separatelyenumerated, merely for clarity, the primary stage 210 of the amplifier200 may also include a first and second portion, relating to the twoportions of the differential signal. The depicted terminal connections,like other connections disclosed herein, may correspond to a pin,landing, control collapse chip connection, other chip connection, or anintermediate signal of a semiconductor device.

At a primary stage 210 of the amplifier 200, a pair of input signalports 202 A-B introduce an input signal (depicted as a differentialinput signal) to the gates of two transistors being configured toproduce a signal gain (e.g., a voltage or current gain). A pair ofcommon mode reference input ports 204 receive a desired referencevoltage at the gates of two additional transistors. The referencevoltage may be a DC voltage which is a reference ground or offsettherefrom, an AC sinusoidal voltage, or another reference common modevoltage. Although not depicted, the signals may be introduced to thegates of the respective transistors via an intermediate element, such asan inductor, series resistance, filter, fuse, protection diode, etc. Thelack of any such intermediate elements is merely for clarity andsimplicity of the figure, and is not intended to limit the disclosure.The common mode voltage is passed, by direct coupling, to an output ofthe primary stage of the amplifier 206 A-B (i.e., an inter-stageoutput), such that the output of the primary stage 206 A-B is caused tocompensate for common mode interference which is thereby introduced tothe amplifier by direct coupling. An “inter-stage output” may refer to ajunction between two stages of an amplifier, according to someembodiments. For example, the junction can include a conductor such as acopper or aluminum interconnect joining the stages of the output. Theinter-stage output may also referred to as an inter-stage input for acorresponding stage of the amplifier. For example, in the depictedembodiment, the input signal ports 202 and the common mode referenceinput ports 204 are delivered to the gates of pairs of respectivetransistors, and the respective transistor pairs are disposed inline,such that the two transistors pass the same current. In the depictedembodiment, no capacitively coupled feedback is provided at said inputports.

Various connections from resistor pairs 252A-B, corresponding to thecommon mode feedback impedance network 150C of FIG. 1 , may be receivedat one or more pairs of feedback inputs 253 A-B. Such feedback inputs253 A-B can intermediate or share a node with the input signal ports 202or the common mode reference input ports 204. The associated resistorpairs 252 may include multiple instances thereof, or may depict variousconnections to a same resistor pair (e.g., resistor pair 152).

Referring now to an additional stage 220 of the amplifier 200,relatively high frequency components of the amplifier output comprisingthe common mode signal are capacitively coupled into current sourcesassociated with (e.g., biasing) a class AB amplifier mesh 208 bycapacitor pairs 254A-B. Such current sources may also be referred to ascurrent mirrors. Similar inputs are introduced at a generallysymmetrical circuit by capacitor pairs 254C-D, such that the common modefeedback is introduced to each of a side of the differential output. Forexample, high side current sources 222A-B, can couple the additionalstage 220 of the amplifier to a supply voltage; low side current sources222A-B can couple the additional stage 220 of the amplifier to areference voltage. The class AB amplifier meshes 208 A-B may compriseadditional amplification circuits/stages and/or biasing elements (e.g.,resistors, diodes, and the like) intended to control the operation ofanother stage of an amplifier, such as an output stage. The second stagemay receive high frequency common mode feedback via capacitor pairs 254A-D. The various capacitor pairs 254 A-D may be a plurality of instancesof a common mode feedback network (or, as discussed above, may bemultiple depictions of connections from the same node) and may bereceived at one or more pairs of feedback inputs 255 A-D.

In many embodiments, at least a portion of the resistor pair feedbackinputs 253 and/or capacitor pair feedback inputs are at different nodesof the amplifier 200, as is depicted. For example, the capacitor pairinput can be disposed symmetrically across the additional stage 220 ofthe amplifier 200, within each differential side of the amplifier. Putdifferently, the capacitor pairs 254 can coupled to a voltage sourcegate and ground gate to cause the voltage source or ground gate tosource or sink current therefrom, responsive to the feedbackcapacitively coupled through the capacitor pairs 254. Such pair may besymmetrically connected to each of a first 220A and second additionalstage portion 220B of the differential amplifier 200.

As described herein, the additional stage 220 (e.g., a second stageand/or output stage of the amplifier 200), receives an input from theprimary stage 210 (e.g., directly, or through intermediate stages orcomponents) at an inter-stage input (i.e., the inter-stage output of theprimary phase). The inter-stage input comprises the relatively lowfrequency common mode signals, as well as the relatively high frequencycommon mode signals at the gate transistor (e.g., through currentbiasing sources, the Class AB meshes 208, etc.) Thus, the additionalstage 220 receives an input from the primary stage 210 having beenconditioned by both the directly and capacitively coupled feedbacksignals.

The depicted amplifier is merely illustrative of an embodiment of thisdisclosure, and the implementation details are not intended to belimiting. Indeed, elements of the present disclosure may be practicedwith various amplifiers. For example, any of the depicted transistorsmay be replaced with a Darlington pair, respective positions of thetransistor pairs may be reversed, additional or fewer stages may beutilized, or the amplifier may include various transistors technologiesand topologies (e.g., bipolar junction transistor (BJT), field effecttransistor (FET), etc.). In some embodiments, two non-differentialsignals may be a victim of a common mode aggressor signal, and thepresent disclosure may be practiced to compensate for said common modeaggressor signal.

In some embodiments, such as where low frequency common modeinterference is not present or not problematic, the direct coupledfeedback portion may be omitted. Likewise, in applications where highfrequency common mode interference is not present or not problematic,the capacitive coupled feedback portions may be omitted. Further,various references to a ground throughout this disclosure may beunderstood as a relative term and do not necessarily designate anyparticular ground (e.g., earth ground, chassis ground, etc.) Indeed, insome embodiments having a differential supply voltage (e.g., +V_(cc) and−V_(cc)) one supply voltage may be designated as a local ground, whichmay simplify consideration and representation of the circuit. Further,it may be convenient to refer to multiple potentials as grounds indiffering contexts, such that grounds discussed herein may be atdifferent potentials.

Each of the primary amplifier stage 210 and additional amplifier stages220 may be configured with a same or varying gain or bandwidth. Forexample, the gain of the first stage of the amplifier can be higher thanan additional stage 220 of the amplifier, which may reduce an inputcurrent (e.g., increase input impedance which may avoid a distortion ofinput signals). A gain can be selected such that a range of frequencieswherein the current through the resistor pairs 252 A-D is not dominatedby the current through the capacitor pairs 254 A-D is amplified by theprimary amplifier stage 210. A gain of an additional amplifier stage 220may be lower than the first stage. For example, a gain may be selectedto avoid a non-linearity of amplification (e.g., high frequency inputsignals received via the capacitor pairs may be amplified). Putdifferently, a gain can be selected such that a range of frequencieswherein the current through the capacitor pairs 254 A-D is not dominatedby the current through the resistor pairs 252 A-D. Corresponding to thereduced gain, the bandwidth of the additional stage 220 may exceed thebandwidth of the primary stage 210.

FIG. 3 is an illustration of an embodiment of a single ended amplifiercircuit 300, intended to highlight the signal path of the relatively lowfrequency common mode component of a feedback signal. For example, FIG.3 may be a simplified or reduced representation of the differentialamplifier 200 of FIG. 2 . Circuit portions of particular interest areshown and identified. The remaining circuit portions are may be lesscritical or can be neglected when considering certain low frequencysignals. Said remaining circuit portions are shown bounded by delimitinglines 350.

An output 305 of the amplifier circuit 300 carries a signal having acommon mode component, such as due to interference coupled onto atransmission cable. That signal is passed through one or more resistors310 (e.g., disposed symmetrically between a differential pair to removea differential component of the signal), which may damp the common modecomponent. The signal is coupled to a primary amplifier stage, such thatthe common mode current flowing to the primary stage 315 passes to anadditional stage (through an inter-stage output). The additional stagemay comprise further voltage and/or current amplification, such as bypassing the common mode current flowing to the primary stage 315 to thegate of a transistor 320 A-B, directly or through a mesh 325. The mesh325 may comprise biasing resistors and/or diodes, additionalamplification stages, other feedback inputs, etc. At sufficiently lowfrequencies, the magnitude of a signal passed through the resistors maybe substantially greater than (e.g., at least one order of magnitude) amagnitude of a signal capacitively coupled through the capacitors. Thus,the circuit operation of the circuits of FIG. 1 , or 2 can beapproximated by disregarding the capacitors. As described above, in someembodiments such capacitors can be omitted for designs which may not besensitive or proximal to high frequency signals.

FIG. 4 depicts an embodiment of a single ended amplifier circuit 400intended to highlight the signal path of the relatively high frequencycommon mode component of a feedback signal. For example, FIG. 4 may be asimplified or reduced representation of the amplifier of FIG. 2 .Circuit portions of particular interest are shown and identified. Theremaining circuit portions are may be less critical or can be neglectedwhen considering certain high frequency signals. Said remaining circuitportions are shown bounded by delimiting lines 350.

An output 405 of the amplifier circuit 400 carries a signal having acommon mode component, such as due to interference coupled onto atransmission cable. That signal is passed through one or more capacitors410 (e.g., disposed symmetrically between a differential pair so as toremove a differential component of the signal). The signal iscapacitively coupled to a pair of current supplies 420 A-B, which areconnected to the gate of a transistor 425 A-B, (e.g., at an output stageof the amplifier 400). The transistor outputs may thereafter be gated byone or more additional transistors, such that a signal from a firsttransistor gate 425A sources current during times of positive operation,and a signal from a second transistor gate 425B sinks current duringtimes of negative operation to complete a desired waveform. Atsufficiently high frequencies, the magnitude of a signal passed throughthe resistors may be substantially less than (e.g., at least one orderof magnitude) a magnitude of a signal capacitively coupled through thecapacitors. Thus, the circuit operation of the circuits of FIG. 1 , or 2can be approximated by disregarding the resistors at certainfrequencies. As described above, in some embodiments, such resistors canbe omitted for designs which may not be sensitive or proximal to lowfrequency signals.

A class AB mesh 430 may comprise various biasing components in order tocontrol the phase of operation of each of the transistors 425 A-B, suchthat the waveform is constructed which may be received by anotherdevice, (e.g., a complete or partial sinusoidal form). In someembodiments, the common mode currents 415 A-B may be further damped,amplified, biased, or otherwise conditioned by the Class AB mesh 430. Insome embodiments, the Class AB mesh may be substantially symmetricalsuch that the path of the common mode signal through the mesh may belimited.

Referring now to FIG. 5 , a method 500 for common mode suppression ispresented, according to some embodiments. In brief summary, the method500 includes receiving a differential data signal at operation 502. Atoperation 504, a common mode reference signal can be received. Atoperation 506, a first differential feedback input is received by afirst stage of an amplifier. At operation 508, a differentialinter-stage output is generated. At operation 510, a second differentialfeedback is received at a second stage of the amplifier. At operation512, a third differential feedback is received at the second stage ofthe amplifier. At operation 514, an output is generated. According tovarious embodiments, the operations described herein can be performed invarious sequences, or operations can be added, omitted, substituted ormodified. The method 500 can be employed with amplifiers disclosedherein, or other amplifiers. For example, the method 500 can be employedwith different a common mode signal coupled to two single ended outputs.

Referring again to operation 502, a differential data signal isreceived. The differential data signal can include a digital or analogsignal. For example, the differential data signal can be received from atwisted cable pair traversing an automotive vehicle (e.g., automotiveEthernet). The differential data signal can couple into the first inputgates of an amplifier, such as directly from a transmission line orthrough a termination network. For example, the differential data signalcan pass through transmission line termination proximal to the amplifierand to input terminals 202 therefrom. The first input gates can be agate of a FET. The differential data signal can include common modedisturbances from other data or power signals of a vehicle.

Referring again to operation 504, a common mode reference signal can bereceived. For example, the common mode reference signal can be a DCvoltage which is a reference ground or offset therefrom, an ACsinusoidal voltage, or another reference common mode voltage. The commonmode input signal can be received at a gate of a FET. Said FET canconnect a drain or source to a drain or source of the FET discussed withregard to operation 502.

Referring again to operation 506, first differential feedback input isreceived by a first stage of an amplifier. For example, the differentialfeedback input can be received intermediate to the first input gates ofan amplifier and a common mode reference signal input. Put differently,the first differential feedback input can be connected to the junctionof the respective source and drain of the FETs discussed with regard tooperations 502 and 504. The differential feedback input can pass througha common mode feedback impedance network 150C, such as a resistor pair152 thereof. The received differential data signal may vary from acommon mode signal passed over the transmission line. For example, thedifferential feedback input received at the first stage of the amplifiermay bias low frequency content of the common mode signal relative tohigh frequency signals which may be damped.

Referring again to operation 508, a differential inter-stage output isgenerated. For example, the inter-stage output can include a receiveddifferential signal including compensation for at least a portion of acommon mode signal coupled there-into. For example, the inter-stageoutput can amplify the incoming signal and retain a portion of highfrequency common mode signal which can thereafter be mitigated atoperations 510 and 512.

Referring again to operations 510 and 512, second and third differentialfeedback inputs are received at the second stage of the amplifier. Forexample, the second and third differential feedback can correspond tocapacitor pairs 154 coupling high frequency portions of the common modesignal. The second and third differential feedback inputs can adjust acurrent source biasing the second stage of the amplifier (e.g., though aclass AB mesh such as a diode or resistor biasing element). Thus, thesecond stage of the amplifier can receive the signal from the firststage, and mitigate high frequency components of the common mode signalcoupled to the signal.

Referring again to operation 514, an output is generated. The output canbe generated by an output stage of the amplifier which can includefurther voltage gain, current gain, or otherwise generate an outputsignal at a voltage level and drive strength to interface with apredefined signal level. In various embodiments, the output stage can bea separate stage from the first and second stage, or can be, forexample, the second stage.

B. Computing and Network Environment

Having discussed specific embodiments of the present solution, it may behelpful to describe aspects of the operating environment as well asassociated system components (e.g., hardware elements) in connectionwith the methods and systems described herein. Referring to FIG. 6A, anembodiment of a network environment is depicted. In brief overview, thenetwork environment includes a wireless communication system thatincludes one or more access points 606, one or more wirelesscommunication devices 602 and a network hardware component 692. Thewireless communication devices 602 may for example include laptopcomputers 602, tablets 602, personal computers 602 and/or cellulartelephone devices 602. The details of an embodiment of each wirelesscommunication device and/or access point are described in greater detailwith reference to FIGS. 6B and 6C. The network environment can be an adhoc network environment, an infrastructure wireless network environment,a subnet environment, etc. in one embodiment

The access points (APs) 606 may be operably coupled to the networkhardware 692 via local area network connections. The network hardware692, which may include a router, gateway, switch, bridge, modem, systemcontroller, appliance, etc., may provide a local area network connectionfor the communication system. Each of the access points 606 may have anassociated antenna or an antenna array to communicate with the wirelesscommunication devices 602 in its area. The wireless communicationdevices 602 may register with a particular access point 606 to receiveservices from the communication system (e.g., via a SU-MIMO or MU-MIMOconfiguration). For direct connections (e.g., point-to-pointcommunications), some wireless communication devices 602 may communicatedirectly via an allocated channel and communications protocol. Some ofthe wireless communication devices 602 may be mobile or relativelystatic with respect to the access point 606.

In some embodiments an access point 606 includes a device or module(including a combination of hardware and software) that allows wirelesscommunication devices 602 to connect to a wired network using Wi-Fi, orother standards. An access point 606 may sometimes be referred to as anwireless access point (WAP). An access point 606 may be configured,designed and/or built for operating in a wireless local area network(WLAN). An access point 606 may connect to a router (e.g., via a wirednetwork) as a standalone device in some embodiments. In otherembodiments, an access point can be a component of a router. An accesspoint 606 can provide multiple devices 602 access to a network. Anaccess point 606 may, for example, connect to a wired Ethernetconnection and provide wireless connections using radio frequency linksfor other devices 602 to utilize that wired connection. An access point606 may be built and/or configured to support a standard for sending andreceiving data using one or more radio frequencies. Those standards, andthe frequencies they use may be defined by the IEEE (e.g., IEEE 802.11standards). An access point may be configured and/or used to supportpublic Internet hotspots, and/or on an internal network to extend thenetwork's Wi-Fi signal range.

In some embodiments, the access points 606 may be used for (e.g.,in-home or in-building) wireless networks (e.g., IEEE 802.11, Bluetooth,ZigBee, any other type of radio frequency based network protocol and/orvariations thereof). Each of the wireless communication devices 602 mayinclude a built-in radio and/or is coupled to a radio. Such wirelesscommunication devices 602 and /or access points 606 may operate inaccordance with the various aspects of the disclosure as presentedherein to enhance performance, reduce costs and/or size, and/or enhancebroadband applications. Each wireless communication devices 602 may havethe capacity to function as a client node seeking access to resources(e.g., data, and connection to networked nodes such as servers) via oneor more access points 606.

The network connections may include any type and/or form of network andmay include any of the following: a point-to-point network, a broadcastnetwork, a telecommunications network, a data communication network, acomputer network. The topology of the network may be a bus, star, orring network topology. The network may be of any such network topologycapable of supporting the operations described herein. In someembodiments, different types of data may be transmitted via differentprotocols. In other embodiments, the same types of data may betransmitted via different protocols.

The communications device(s) 602 and access point(s) 606 may be deployedas and/or executed on any type and form of computing device, such as acomputer, network device or appliance capable of communicating on anytype and form of network and performing the operations described herein.FIGS. 6B and 6C depict block diagrams of a computing device 600 usefulfor practicing an embodiment of the wireless communication devices 602or the access point 606. As shown in FIGS. 6B and 6C, each computingdevice 600 includes a central processing unit 621, and a main memoryunit 622. As shown in FIG. 6B, a computing device 600 may include astorage device 628, an installation device 616, a network interface 618,an I/O controller 623, display devices 624 a-624 n, a keyboard 626 and apointing device 627, such as a mouse. The storage device 628 mayinclude, without limitation, an operating system and/or software. Asshown in FIG. 6C, each computing device 600 may also include additionaloptional elements, such as a memory port 603, a bridge 670, one or moreinput/output devices 630 a-630 n (generally referred to using referencenumeral 630), and a cache memory 640 in communication with the centralprocessing unit 621.

The central processing unit 621 is any logic circuitry that responds toand processes instructions fetched from the main memory unit 622. Inmany embodiments, the central processing unit 621 is provided by amicroprocessor unit, such as: those manufactured by Intel Corporation ofMountain View, California; those manufactured by International BusinessMachines of White Plains, New York; or those manufactured by AdvancedMicro Devices of Sunnyvale, California. The computing device 600 may bebased on any of these processors, or any other processor capable ofoperating as described herein.

Main memory unit 622 may be one or more memory chips capable of storingdata and allowing any storage location to be directly accessed by themicroprocessor 621, such as any type or variant of Static random accessmemory (SRAM), Dynamic random access memory (DRAM), Ferroelectric RAM(FRAM), NAND Flash, NOR Flash and Solid State Drives (SSD). The mainmemory 622 may be based on any of the above described memory chips, orany other available memory chips capable of operating as describedherein. In the embodiment shown in FIG. 6B, the processor 621communicates with main memory 622 via a system bus 650 (described inmore detail below). FIG. 6C depicts an embodiment of a computing device600 in which the processor communicates directly with main memory 622via a memory port 603. For example, in FIG. 6C the main memory 622 maybe DRDRAM.

FIG. 6C depicts an embodiment in which the main processor 621communicates directly with cache memory 640 via a secondary bus,sometimes referred to as a backside bus. In other embodiments, the mainprocessor 621 communicates with cache memory 640 using the system bus650. Cache memory 640 typically has a faster response time than mainmemory 622 and is provided by, for example, SRAM, BSRAM, or EDRAM. Inthe embodiment shown in FIG. 6C, the processor 621 communicates withvarious I/O devices 630 via a local system bus 650. Various buses may beused to connect the central processing unit 621 to any of the I/Odevices 630, for example, a VESA VL bus, an ISA bus, an EISA bus, aMicroChannel Architecture (MCA) bus, a PCI bus, a PCI-X bus, aPCI-Express bus, or a NuBus. For embodiments in which the I/O device isa video display 624, the processor 621 may use an Advanced Graphics Port(AGP) to communicate with the display 624. FIG. 6C depicts an embodimentof a computer 600 in which the main processor 621 may communicatedirectly with I/O device 630 b, for example via HYPERTRANSPORT, RAPIDIO,or INFINIBAND communications technology. FIG. 6C also depicts anembodiment in which local busses and direct communication are mixed: theprocessor 621 communicates with I/O device 630 a using a localinterconnect bus while communicating with I/O device 630 b directly.

A wide variety of I/O devices 630 a-630 n may be present in thecomputing device 600. Input devices include keyboards, mice, trackpads,trackballs, microphones, dials, touch pads, touch screen, and drawingtablets. Output devices include video displays, speakers, inkjetprinters, laser printers, projectors and dye-sublimation printers. TheI/O devices may be controlled by an I/O controller 623 as shown in FIG.6B. The I/O controller may control one or more I/O devices such as akeyboard 626 and a pointing device 627, e.g., a mouse or optical pen.Furthermore, an I/O device may also provide storage and/or aninstallation medium 616 for the computing device 600. In still otherembodiments, the computing device 600 may provide USB connections (notshown) to receive handheld USB storage devices such as the USB FlashDrive line of devices manufactured by Twintech Industry, Inc. of LosAlamitos, California.

Referring again to FIG. 6B, the computing device 600 may support anysuitable installation device 616, such as a disk drive, a CD-ROM drive,a CD-R/RW drive, a DVD-ROM drive, a flash memory drive, tape drives ofvarious formats, USB device, hard-drive, a network interface, or anyother device suitable for installing software and programs. Thecomputing device 600 may further include a storage device, such as oneor more hard disk drives or redundant arrays of independent disks, forstoring an operating system and other related software, and for storingapplication software programs such as any program or software 620 forimplementing (e.g., configured and/or designed for) the systems andmethods described herein. Optionally, any of the installation devices616 could also be used as the storage device. Additionally, theoperating system and the software can be run from a bootable medium.

Furthermore, the computing device 600 may include a network interface618 to interface to the network 604 through a variety of connectionsincluding, but not limited to, standard telephone lines, LAN or WANlinks (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadbandconnections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet,Ethernet-over-SONET), wireless connections, or some combination of anyor all of the above. Connections can be established using a variety ofcommunication protocols (e.g., TCP/IP, IPX, SPX, NetBIOS, Ethernet,ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax and direct asynchronousconnections). In one embodiment, the computing device 600 communicateswith other computing devices 600′ via any type and/or form of gateway ortunneling protocol such as Secure Socket Layer (SSL) or Transport LayerSecurity (TLS). The network interface 618 may include a built-in networkadapter, network interface card, PCMCIA network card, card bus networkadapter, wireless network adapter, USB network adapter, modem or anyother device suitable for interfacing the computing device 600 to anytype of network capable of communication and performing the operationsdescribed herein.

In some embodiments, the computing device 600 may include or beconnected to one or more display devices 624 a-624 n. As such, any ofthe I/O devices 630 a-630 n and/or the I/O controller 623 may includeany type and/or form of suitable hardware, software, or combination ofhardware and software to support, enable or provide for the connectionand use of the display device(s) 624 a-624 n by the computing device600. For example, the computing device 600 may include any type and/orform of video adapter, video card, driver, and/or library to interface,communicate, connect or otherwise use the display device(s) 624 a-624 n.In one embodiment, a video adapter may include multiple connectors tointerface to the display device(s) 624 a-624 n. In other embodiments,the computing device 600 may include multiple video adapters, with eachvideo adapter connected to the display device(s) 624 a-624 n. In someembodiments, any portion of the operating system of the computing device600 may be configured for using multiple displays 624 a-624 n. Acomputing device 600 may be configured to have one or more displaydevices 624 a-624 n.

In further embodiments, an I/O device 630 may be a bridge between thesystem bus 650 and an external communication bus, such as a USB bus, anApple Desktop Bus, an RS-232 serial connection, a SCSI bus, a FireWirebus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a GigabitEthernet bus, an Asynchronous Transfer Mode bus, a FibreChannel bus, aSerial Attached small computer system interface bus, a USB connection,or a HDMI bus.

A computing device 600 of the sort depicted in FIGS. 6B and 6C mayoperate under the control of an operating system, which controlscheduling of tasks and access to system resources. The computing device600 can be running any operating system such as any of the versions ofthe MICROSOFT WINDOWS operating systems, the different releases of theUnix and Linux operating systems, any version of the MAC OS forMacintosh computers, any embedded operating system, any real-timeoperating system, any open source operating system, any proprietaryoperating system, any operating systems for mobile computing devices, orany other operating system capable of running on the computing deviceand performing the operations described herein. Typical operatingsystems include, but are not limited to: Android, produced by GoogleInc.; WINDOWS 7 and 8, produced by Microsoft Corporation of Redmond,Washington; MAC OS, produced by Apple Computer of Cupertino, California;WebOS, produced by Research In Motion (RIM); OS/2, produced byInternational Business Machines of Armonk, New York; and Linux, afreely-available operating system distributed by Caldera Corp. of SaltLake City, Utah, or any type and/or form of a Unix operating system,among others.

The computer system 600 can be any workstation, telephone, desktopcomputer, laptop or notebook computer, server, handheld computer, mobiletelephone or other portable telecommunications device, media playingdevice, a gaming system, mobile computing device, or any other typeand/or form of computing, telecommunications or media device that iscapable of communication. The computer system 600 has sufficientprocessor power and memory capacity to perform the operations describedherein.

In some embodiments, the computing device 600 may have differentprocessors, operating systems, and input devices consistent with thedevice. For example, in one embodiment, the computing device 600 is asmart phone, mobile device, tablet or personal digital assistant. Instill other embodiments, the computing device 600 is an Android-basedmobile device, an iPhone smart phone manufactured by Apple Computer ofCupertino, California, or a Blackberry or WebOS-based handheld device orsmart phone, such as the devices manufactured by Research In MotionLimited. Moreover, the computing device 600 can be any workstation,desktop computer, laptop or notebook computer, server, handheldcomputer, mobile telephone, any other computer, or other form ofcomputing or telecommunications device that is capable of communicationand that has sufficient processor power and memory capacity to performthe operations described herein.

Although the disclosure may reference one or more “users”, such “users”may refer to user-associated devices or stations (STAs), for example,consistent with the terms “user” and “multi-user” typically used in thecontext of a multi-user multiple-input and multiple-output (MU-MIMO)environment.

Although examples of communications systems described above may includedevices and APs operating according to an 802.11 standard, it should beunderstood that embodiments of the systems and methods described canoperate according to other standards and use wireless communicationsdevices other than devices configured as devices and APs. For example,multiple-unit communication interfaces associated with cellularnetworks, satellite communications, vehicle communication networks, andother non-802.11 wireless networks can utilize the systems and methodsdescribed herein to achieve improved overall capacity and/or linkquality without departing from the scope of the systems and methodsdescribed herein.

It should be noted that certain passages of this disclosure mayreference terms such as “first” and “second” in connection with devices,mode of operation, transmit chains, antennas, etc., for purposes ofidentifying or differentiating one from another or from others. Theseterms are not intended to merely relate entities (e.g., a first deviceand a second device) temporally or according to a sequence, although insome cases, these entities may include such a relationship. Nor do theseterms limit the number of possible entities (e.g., devices) that mayoperate within a system or environment.

It should be understood that the systems described above may providemultiple ones of any or each of those components and these componentsmay be provided on either a standalone machine or, in some embodiments,on multiple machines in a distributed system. In addition, the systemsand methods described above may be provided as one or morecomputer-readable programs or executable instructions embodied on or inone or more articles of manufacture. The article of manufacture may be afloppy disk, a hard disk, a CD-ROM, a flash memory card, a PROM, a RAM,a ROM, or a magnetic tape. In general, the computer-readable programsmay be implemented in any programming language, such as LISP, PERL, C,C++, C#, PROLOG, or in any byte code language such as JAVA. The softwareprograms or executable instructions may be stored on or in one or morearticles of manufacture as object code.

The term “coupled” and variations thereof, as used herein, means theconnection of two elements directly or indirectly to one another. Suchconnections may be achieved with two elements coupled directly to eachother, with the two elements coupled to each other using a separateintervening member and any additional intermediate elements coupled withone another, or with the two elements coupled to each other using anintervening member that is integrally formed as a single unitary bodywith one of the two elements. If “coupled” or variations thereof aremodified by an additional term (e.g., directly coupled), the genericdefinition of “coupled” provided above is modified by the plain languagemeaning of the additional term (e.g., “directly coupled” means thejoining of two elements without any separate intervening member),resulting in a narrower definition than the generic definition of“coupled” provided above. Such coupling may be mechanical, electrical,or fluidic.

While the foregoing written description of the methods and systemsenables one of ordinary skill to make and use what is consideredpresently to be the best mode thereof, those of ordinary skill willunderstand and appreciate the existence of variations, combinations, andequivalents of the specific embodiment, method, and examples herein. Thepresent methods and systems should therefore not be limited by the abovedescribed embodiments, methods, and examples, but by all embodiments andmethods within the scope and spirit of the disclosure.

We claim:
 1. A device, comprising: an amplifier, comprising: a firstamplifier stage, comprising: a pair of first input ports configured toreceive a differential input signal at a first pair of gates of a firstpair of transistors, a pair of second input ports configured to receivea common mode reference at a second pair of gates of a second pair oftransistors, and a first pair of inter-stage outputs configured todeliver a pair of amplified signals from the first amplifier stage to apair of gates of a third pair of transistors of a second amplifierstage; and the second amplifier stage, comprising: a first pair ofcurrent sources, and a second pair of current sources, a feedbacknetwork coupled between an output of the amplifier and a stage of theamplifier, the feedback network comprising: a first pair of feedbackinputs directly coupled to the first amplifier stage, or a second pairof feedback inputs capacitively coupled to the first pair of currentsources, or a third pair of feedback inputs capacitively coupled to thesecond pair of current sources.
 2. The device of claim 1, wherein thefeedback network comprises: the first pair of feedback inputs directlycoupled to the first amplifier stage; and the second pair of feedbackinputs capacitively coupled to the first pair of current sources; andthe third pair of feedback inputs capacitively coupled to the secondpair of current sources.
 3. The device of claim 2, wherein: each of thefirst pair of feedback inputs, the second pair of feedback inputs, andthe third pair of feedback inputs couple to the output of the amplifierproximal to the amplifier relative to a termination network of atransmission line coupled thereto.
 4. The device of claim 2, wherein: again of the first amplifier stage exceeds a gain of the second amplifierstage; and a bandwidth of the second amplifier stage exceeds a bandwidthof the first amplifier stage.
 5. The device of claim 2, wherein: thefeedback network and the amplifier are integral to a same semiconductordevice.
 6. The device of claim 2, wherein: the amplifier is integral toa semiconductor device configured to interface with the feedback networkcomprising a discrete resistor pair and a discrete capacitor pair. 7.The device of claim 3, wherein: the termination network includes acommon mode choke and a low pass filter.
 8. The device of claim 1,wherein: the first pair of feedback inputs, the second pair of feedbackinputs, or the third pair of feedback inputs connect to the output ofthe amplifier proximal to the amplifier relative to a terminationnetwork of a transmission line coupled thereto, the transmission linecomprising an unshielded twisted pair corresponding to the output of theamplifier; and the termination network includes a common mode choke anda low pass filter.
 9. A system, comprising: a first amplifier stage ofan amplifier, comprising: a pair of first input ports configured toreceive a differential input signal at a first pair of gates of a firstpair of transistors, a pair of second input ports configured to receivea common mode reference at a second pair of gates of a second pair oftransistors, and a first pair of inter-stage outputs configured todeliver a pair of amplified signals from the first amplifier stage to apair of gates of a third pair of transistors of a second amplifierstage; and the second amplifier stage, comprising: a first pair of highside current sources, and a second pair of low side current sources, afeedback network coupled between an output of the amplifier and a stageof the amplifier, the feedback network comprising: a first pair offeedback inputs directly coupled to the first amplifier stage; a secondpair of feedback inputs capacitively coupled to the first pair of highside current sources; and a third pair of feedback inputs capacitivelycoupled to the second pair of low side current sources.
 10. The systemof claim 9, wherein: each of the first pair of feedback inputs, thesecond pair of feedback inputs, and the third pair of feedback inputsconnect to the output of the amplifier proximal to the amplifierrelative to a termination network of a transmission line coupledthereto.
 11. The system of claim 9, wherein: a gain of the firstamplifier stage exceeds a gain of the second amplifier stage; and abandwidth of the second amplifier stage exceeds a bandwidth of the firstamplifier stage.
 12. The system of claim 9, wherein: the feedbacknetwork and the amplifier are integral to a same semiconductor device.13. The system of claim 9, wherein: the amplifier is integral to asemiconductor device configured to interface with the feedback networkcomprising a discrete resistor pair and a discrete capacitor pair. 14.The system of claim 10, wherein: the termination network includes acommon mode choke and a low pass filter.
 15. A method, comprising:receiving, at a first stage of an amplifier: a differential data signalat first input gates of first transistors of respective portions of thefirst stage; a common mode reference signal at second input gates ofsecond transistors of respective portions of the first stage; and afirst differential feedback input at third inputs intermediate to thefirst transistors and the second transistors; generating, by the firststage of the amplifier: a differential inter-stage output based on thedifferential data signal, the common mode reference signal, and thefirst differential feedback input; receiving, by a second stage of theamplifier: a second differential feedback input at a high side currentsource at respective portions of the second stage; a third differentialfeedback input at a low side current source at respective portions ofthe second stage, wherein the differential inter-stage outputintermediate to the high side current source and the low side currentsource at respective portions of the second stage; generating, by thesecond stage of the amplifier, an output based on the differentialinter-stage output, the second differential feedback input, and thethird differential feedback input.
 16. The method of claim 15, wherein:each of the first differential feedback input, the second differentialfeedback input, and the third differential feedback input connect to theoutput of the amplifier proximal to the amplifier relative to atermination network of a transmission line coupled thereto.
 17. Themethod of claim 15, wherein: a gain of the first stage exceeds a gain ofthe second stage; and a bandwidth of the second stage exceeds abandwidth of the first stage.
 18. The method of claim 15, wherein: theamplifier and a feedback network are integral to a same semiconductordevice, the feedback network coupling the output of the amplifier to thefirst differential feedback input, the second differential feedbackinput, and the third differential feedback input.
 19. The method ofclaim 15, wherein: the amplifier is integral to a semiconductor deviceconfigured to interface with a feedback network comprising a discreteresistor pair and a discrete capacitor pair.
 20. The method of claim 16,wherein: the termination network includes a common mode choke and a lowpass filter.